All digital systems use timing devices such as latches and flip-flops as part of the digital systems. As the operating frequencies increase and the number of logic gates between timing elements are reduced, timing constraints are reflected on the design of flip-flops. Additionally, low delay from the clock input to data output, shorter setup and hold times are required. Other critical elements of high-speed latch design are low-power operation, small size and low clock load.
The prior art has presented many flip-flop structures. One such flip-flop structure is illustrated in FIG. 1. This flip-flop has a first stage 102 and a second stage 104. The second stage 104 includes a R-S latch. The first stage 102 of this flip-flop includes a sense amplifier which is widely used in memory integrated circuits. Differential inputs of the first stage 102 sense the difference between the inputs. The inputs can be obtained from either a dual or single-rail logic. With single-rail logic, a complementary output can be generated by use of an inverter. This sense amplifier stage produces monotonous transitions from the high to low logic levels at nodes S and R on the leading clock edge and the S-R latch captures each monotonous transition and holds the state until the next leading clock edge arrives. Thus, the whole structure operates as a flip-flop.
The S-R latch operates such that the input S is a set input and R is a reset input. The low level at both S and R inputs are not permitted and that is prevented by the sense-amplifier stage 102. The low level at S sets the Q output to high, which in turn forces the Q to low. Conversely, the low level at R sets the Q to high, which in turn forces Q to low. Thus, one of the outputs is always delayed with respect to the other. The rising edge always occurs first, after one gate delay, and the falling edge occurs after two gate delays. And the worst of two delays has to be taken into account when calculating the maximum operating clock frequency. This limits the performance of prior art sense-amplifier flip-flops.